The present invention generally relates to a memory apparatus, and more particularly to a serial-access memory apparatus having precharging units, in which data is serially written to and read from a plurality of memory cells arranged in a matrix formation.
In digital processing systems, FIFO (first-in, first-out) memory devices are commonly used to store information (for example, digital image signals). FIG. 1 shows a FIFO memory device according to the prior art. The FIFO memory device shown in FIG. 1 includes a memory cell array 10 in which sixty-four memory cells MCmn (m=0, . . . , 7; n=0, . . . , 7), each of which stores 1-bit data, are arranged in an 8.times.8 matrix formation, a writing unit 20 for writing serial input data DI to the memory cell array 10, a write address pointer 21 for pointing to a specific location of the memory cell array 10 (a writing word line WWLn thereof) at which the serial input data DI is written, a reading unit 30 for reading out data DO from the memory cell array 10 and for serially outputting the data DO, and a read address pointer 31 for pointing to a specific location of the memory cell array 10 (a reading word line RWLn thereof) from which the output data DO is read out. In the reading unit 30 of the memory device, a memory sense amplifier (not shown in FIG. 1) senses the output levels of the memory cells of the memory cell array 10 and the measurement of the data in the memory cell array 10 is amplified.
When a reset signal RSTWB with a low level is input, the write address pointer 21 is initialized to reset the writing address of the memory cell array 10 to memory cell MC00. In synchronism with a writing clock WCK, which is input to the write address pointer 21 and the writing unit 20, the memory cell MCmn to which the first piece of the input data DI is written is selected, and the write address pointer 21 outputs a line select signal WBSm to the writing unit 20, the line select signal WBSm indicating the writing bit line WBLm of the memory cell array 10 at which the selected memory cell MCmn is located. Also, in synchronism with the writing clock WCK, the write address pointer 21 outputs a high-level signal to the writing word line WWLn connected to the memory cell MCmn of the memory cell array 10.
When a reset signal RSTRB with a low level is input, the read address pointer 31 is initialized to reset the reading address of the memory cell array 10 to the memory cell MC00. In synchronism with a reading clock RCK (which is input to the read address pointer 31 and the reading unit 30), the memory cell MCmn from which the start piece of the output data DO is read is selected, and the read address pointer 31 outputs a line select signal RBSm to the reading unit 30, the line select signal RBSm indicating the reading bit line RBLm of the memory cell array 10 at which the selected memory cell MCmn is located. Also, in synchronism with the reading clock RCK, the read address pointer 31 outputs a high-level signal to the reading word line RWLn connected to the memory cell MCmn of the memory cell array 10.
In the FIFO memory device described above, in order to quickly read out data from the FIFO memory device, a known precharging method has been used. In this precharging method, precharging units apply an electric voltage to the reading bit lines RBLm before data is read from the memory. For example, Japanese Laid-Open Patent Publication Nos. 1-137491 and 61-271683 disclose such precharging methods which are applied to the FIFO memory device.
FIG. 2 shows the operation of the conventional FIFO memory device shown in FIG. 1 including the above mentioned precharging units. Hereinafter, the term "leading edge of a signal" denotes a signal portion at which the signal changes from the low level to the high level, and "trailing edge of a signal" denotes a signal portion at which the signal changes from the high level to the low level.
In the FIFO memory device shown in FIG. 2, a precharge signal PRC is set to the high level before a reading cycle RCO in which data is read from the memory cell MCmn has started, and all the reading bit lines RBL0 to RBL7 connected to the memory cell array 10 are preset to a prescribed voltage. After a reading clock RCK changes from the low level to the high level, the high-level precharge signal PRC changes to the low level, so that all the precharging of the eight reading bit lines is completed. In response to the trailing edge of the precharge signal PRC, the signal, output from the read address pointer 31 to the reading word line RWLn, changes from the low level to the high level. In response to the leading edge of this signal, the data from the memory cell MCmn connected to the reading word line RWLn is output to the reading bit line RBLm. One of the eight reading bit lines RBL0 to RBL7 is selected by the bit line select signal RBSm from the read address pointer 31. The voltage of the selected bit line is sensed and amplified by the memory sense amplifier of the reading unit 30, so that the output data DO is read out by the reading unit 30. After a sensing end signal appears, the signal output to the reading word line RWLn is reset to the low level. In response to the trailing edge of the reading word line signal, a leading edge of the precharge signal PRC appears so that the precharging of the eight reading bit lines RBL0 to RBL7 is performed in order to serially read out data from the memory cell array 10. In other words, when the reading word line signal changes to the low level, the precharge signal changes to the high level for precharging the eight reading bit lines, and then data is read from the next memory cell MC(m+1)n.
Therefore, in the conventional memory device described above, it is necessary to precharge all the reading bit lines RBL0-RBL7 to the prescribed voltage for reading out data from one of the memory cells of the memory cell array. Also, the conventional memory device uses a relatively large amount of electric power for reading out the data. Thus, for each reading cycle, the conventional memory device requires the access time for reading out the data as well as the precharging time for precharging all the reading bit lines, and the total reading time is relatively long.